1. Field of the Invention
The present invention relates to a semiconductor memory module on which a plurality of semiconductor memories and an interface chip are mounted.
Priority is claimed on Japanese Patent Application No. 2010-042594, Feb. 26, 2010, the content of which is incorporated herein by reference.
2. Description of the Related Art
Recently, synchronous DRAM (SDRAM) synchronized with external clocks has become mainstream in dynamic random access memories (DRAM) which are typical examples of the semiconductor devices. Examples of the synchronous DRAM (SDRAM) may include double data rate (DDR) SDRAM, DDR2 SDRAM and DDR3 SDRAM, to which the DDR technology is introduced in order to perform predetermined operations by synchronizing not only the rising edge of a clock signal but also the falling edge thereof in order to further improve the data transfer rate of the device. In order to realize the DDR technology, two kinds of complementary clock signals are necessary. Here, there are two technologies to generate the two kinds of complementary clock signals. One is that only a first clock signal is supplied from outside the SDRAM and two kinds of internal control clock signals are generated in the SDRAM. The other is that a first clock signal and a second clock signal which has a reverse phase of the first clock signal are supplied from outside the SDRAM and two kinds of internal control clock signals are generated in the SDRAM.
In either technology, the SDRAM utilizing the DDR technology requires a clock signal synchronization circuit that refers to a phase locked loop (PLL) or a delay locked loop (DLL) to synchronize the internal control clock signal to the external clock signal.
Japanese Unexamined Patent Application, First Publication No. JP-A-10-189889 discloses controlling an SDRAM macro chip by a clock signal output from the PLL in the LSI with DRAM (Embedded DRAM).
Japanese Unexamined Patent Application, Second Publication, JP-A-2003-59272 discloses controlling memory banks and I/Os by a clock signal output from the DLL in the SDRAM.
In devices integrating large-capacity semiconductor memories such as personal computers or servers, in order to integrate semiconductor memories at high density, several semiconductor memory modules each having eight to sixteen semiconductor memories like dual inline memory modules (DIMMs) are mounted on a mother board.
FIG. 6 shows a semiconductor memory module 300 according to the related art. The semiconductor memory module 300 has eight semiconductor memories 301 to 308 mounted on the mother board. The eight semiconductor memories are synchronized with clocks which have been input from, for example, an external memory controller via a signal line 321, when the semiconductor memory fetches a command address and performs desired operations.
Further, in data input and output operations, the eight semiconductor memories receive or output an external data signal DQ from or to, for example, external 64-bit bus lines (64 Bit Bus) via a signal line 323 in synchronization with clocks which have been input via the signal line 321.
Japanese Unexamined Patent Application, Third Publication JP-A-9-91206 discloses the memory controller, in which a memory controller with an error correcting code (ECC) function controls four semiconductor memories.